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Switch mode regulators3 }/ h. x7 u% G8 `8 ?; H# N, G" N5 q" c
QCC3040 VFBGA contains two switch mode regulators for optimum power efficiency. These switch mode regulators
4 P3 ], Z3 p& { _( yreceive power from VBAT or VCHG under application software control.
' E3 k" [! h4 I, Y6 L7 M7 p, fThe System SMPS generates the main 1.8 V supply rail, which supplies most of the analog circuits on QCC3040
8 T* Y* ?1 @5 eVFBGA and the flash memory. The System SMPS can supply power to external components.
( ?& E( ^) \) o+ `) _The digital SMPS generates the power for the digital circuits. It is variable voltage and automatically switches
8 [# z# X; R& s# o0 P" ybetween 1.1 V (nominal) and 0.85 V (nominal) in low-power modes.
" ~2 W- j7 W0 ?( SThe SMPS both have three operating modes:, {& J5 p+ e" m, p# h
■ Normal (PWM)
: r. x' v& S; x3 Q$ Y■ Two low-power modes with reduced current capability:, A/ h. q' f g0 X$ K5 q9 x
□ PFM8 E! f7 ~' a1 V3 i
□ ULP
, d) |" l% h* e- ?Normally the system auto switches, but this is optionally disabled.7 ?& ~7 l' ~) }; b% x4 [
The SMPS uses a 4.7 μH inductor and a 4.7 μF output capacitor.
6 ]8 q4 o2 @8 q8 S+ M& a N0 bFor guidance on choice of inductor, capacitor and layout, see QCC3040 VFBGA Hardware Design Guide (80-
, u2 X) F% j) |! GCH285-1).3 G' U8 ~. w' S, c; i# ^/ Q8 E
A single node SMPS_DCPL is a low impedance decoupling point for the inputs to both SMPS. This point must have5 G5 l& Q6 Q- b9 c# [3 A
a 2.2 μF. QTIL recommends using a 100 nF capacitor on the SMPS_DCPL point.
6 j5 O# i4 m6 LThe SMPS Regulators are enabled by a rising edge on SYS_CTRL, or a rising edge on VBAT or presence of VCHG.
6 C' S1 y/ W& G3 q+ d" k! d! T, Q6 _& v* `
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